Verilog HDLtxt,chm,pdf,epub,mobi下载 作者:Samir Palnitkar 出版社: Prentice Hall 副标题: a guide to digital design and synthesis 出版年: 2003-3-3 页数: 496 定价: USD 115.00 装帧: Hardcover ISBN: 9780130449115 内容简介 · · · · · ·Verilog HDL is a language for digital design, just as C is a language for programming. This complete Verilog HDL reference progresses from the basic Verilog concepts to the most advanced concepts in digital design. Palnitkar covers the gamut of Verilog HDL fundamentals, such as gate, RTL, and behavioral modeling, all the way to advanced concepts, such as timing simulation, swit... 作者简介 · · · · · ·About the Author Samir Palnitkar is currently the President of Jambo Systems, Inc., a leading ASIC design and verification services company which specializes in high-end designs for microprocessor, networking, and communications applications. Mr. Palnitkar is a serial entrepreneur. He was the founder of Integrated Intellectual Property, Inc., an ASIC company that was acquired b... 目录 · · · · · ·CopyrightAbout the Author List of Figures List of Tables List of Examples Foreword · · · · · ·() Copyright About the Author List of Figures List of Tables List of Examples Foreword Preface Who Should Use This Book How This Book Is Organized Conventions Used in This Book Acknowledgments Part 1. Basic Verilog Topics Chapter 1. Overview of Digital Design with Verilog HDL Section 1.1. Evolution of Computer-Aided Digital Design Section 1.2. Emergence of HDLs Section 1.3. Typical Design Flow Section 1.4. Importance of HDLs Section 1.5. Popularity of Verilog HDL Section 1.6. Trends in HDLs Chapter 2. Hierarchical Modeling Concepts Section 2.1. Design Methodologies Section 2.2. 4-bit Ripple Carry Counter Section 2.3. Modules Section 2.4. Instances Section 2.5. Components of a Simulation Section 2.6. Example Section 2.7. Summary Section 2.8. Exercises Chapter 3. Basic Concepts Section 3.1. Lexical Conventions Section 3.2. Data Types Section 3.3. System Tasks and Compiler Directives Section 3.4. Summary Section 3.5. Exercises Chapter 4. Modules and Ports Section 4.1. Modules Section 4.2. Ports Section 4.3. Hierarchical Names Section 4.4. Summary Section 4.5. Exercises Chapter 5. Gate-Level Modeling Section 5.1. Gate Types Section 5.2. Gate Delays Section 5.3. Summary Section 5.4. Exercises Chapter 6. Dataflow Modeling Section 6.1. Continuous Assignments Section 6.2. Delays Section 6.3. Expressions, Operators, and Operands Section 6.4. Operator Types Section 6.5. Examples Section 6.6. Summary Section 6.7. Exercises Chapter 7. Behavioral Modeling Section 7.1. Structured Procedures Section 7.2. Procedural Assignments Section 7.3. Timing Controls Section 7.4. Conditional Statements Section 7.5. Multiway Branching Section 7.6. Loops Section 7.7. Sequential and Parallel Blocks Section 7.8. Generate Blocks Section 7.9. Examples Section 7.10. Summary Section 7.11. Exercises Chapter 8. Tasks and Functions Section 8.1. Differences between Tasks and Functions Section 8.2. Tasks Section 8.3. Functions Section 8.4. Summary Section 8.5. Exercises Chapter 9. Useful Modeling Techniques Section 9.1. Procedural Continuous Assignments Section 9.2. Overriding Parameters Section 9.3. Conditional Compilation and Execution Section 9.4. Time Scales Section 9.5. Useful System Tasks Section 9.6. Summary Section 9.7. Exercises Part 2. Advanced VerilogTopics Chapter 10. Timing and Delays Section 10.1. Types of Delay Models Section 10.2. Path Delay Modeling Section 10.3. Timing Checks Section 10.4. Delay Back-Annotation Section 10.5. Summary Section 10.6. Exercises Chapter 11. Switch-Level Modeling Section 11.1. Switch-Modeling Elements Section 11.2. Examples Section 11.3. Summary Section 11.4. Exercises Chapter 12. User-Defined Primitives Section 12.1. UDP basics Section 12.2. Combinational UDPs Section 12.3. Sequential UDPs Section 12.4. UDP Table Shorthand Symbols Section 12.5. Guidelines for UDP Design Section 12.6. Summary Section 12.7. Exercises Chapter 13. Programming Language Interface Section 13.1. Uses of PLI Section 13.2. Linking and Invocation of PLI Tasks Section 13.3. Internal Data Representation Section 13.4. PLI Library Routines Section 13.5. Summary Section 13.6. Exercises Chapter 14. Logic Synthesis with Verilog HDL Section 14.1. What Is Logic Synthesis? Section 14.2. Impact of Logic Synthesis Section 14.3. Verilog HDL Synthesis Section 14.4. Synthesis Design Flow Section 14.5. Verification of Gate-Level Netlist Section 14.6. Modeling Tips for Logic Synthesis Section 14.7. Example of Sequential Circuit Synthesis Section 14.9. Exercises Chapter 15. Advanced Verification Techniques Section 15.1. Traditional Verification Flow Section 15.2. Assertion Checking Section 15.3. Formal Verification Section 15.4. Summary Part 3. Appendices Appendix A. Strength Modeling and Advanced Net Definitions Section A.1. Strength Levels Section A.2. Signal Contention Section A.3. Advanced Net Types Appendix B. List of PLI Routines Section B.1. Conventions Section B.2. Access Routines Section B.3. Utility (tf_) Routines Appendix C. List of Keywords, System Tasks, and Compiler Directives Section C.1. Keywords Section C.2. System Tasks and Functions Section C.3. Compiler Directives Appendix D. Formal Syntax Definition Section D.1. Source Text Section D.2. Declarations Section D.3. Primitive Instances Section D.4. Module and Generated Instantiation Section D.5. UDP Declaration and Instantiation Section D.6. Behavioral Statements Section D.7. Specify Section Section D.8. Expressions Section D.9. General Endnotes Appendix E. Verilog Tidbits Origins of Verilog HDL Interpreted, Compiled, Native Compiled Simulators Event-Driven Simulation, Oblivious Simulation Cycle-Based Simulation Fault Simulation General Verilog Web sites Architectural Modeling Tools High-Level Verification Languages Simulation Tools Hardware Acceleration Tools In-Circuit Emulation Tools Coverage Tools Assertion Checking Tools Equivalence Checking Tools Formal Verification Tools Appendix F. Verilog Examples Section F.1. Synthesizable FIFO Model Section F.2. Behavioral DRAM Model Bibliography Manuals Books Quick Reference Guides About the CD-ROM Using the CD-ROM Technical Support · · · · · · () |
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